In advanced process technology nodes, process (P), voltage (V), and temperature (T) variations (also referred to as “PVT” variations), and aging behavior can degrade performance and reliability of a design. To mitigate these issues, modern microprocessor and/or system-on-chip (SoC) designs add fixed voltage/timing margin guardband or margin to guarantee target performance and reliability of the microprocessor or SoC. Moreover, these PVT variations and aging may be infrequent in nature. Hence, adding guardband or margin to avoid variation-caused errors hurts energy efficiency and performance.